1. Field of the Invention
The present invention generally relates to semiconductor devices; and more particularly, to a semiconductor device having a semiconductor filler provided in grooves.
2. Discussion of the Relevant Art
FIG. 41 is a sectional view of a conventional transistor 102.
The transistor 102 is a trench-type power MOSFET and includes a semiconductor substrate 111 of silicon single crystal doped with a high concentration n+ type impurity and a drain layer 112 including an n− type silicon epitaxial layer formed on the semiconductor substrate 111 by epitaxial growth.
The reference numeral 110 denotes a substrate to be processed having the semiconductor substrate 111 and the drain layer 112. The substrate to be processed 110 is subjected to semiconductor manufacturing process so that a p-type body layer 113 is formed on the inside surface of the drain layer 112 and a plurality of p+ type Ohmic diffusion regions 116 and a plurality of n+ type source diffusion regions 130 are formed in the vicinity of the inside surface of the body layer 113.
The substrate to be processed 110 has its surface etched into strip shapes between the source diffusion regions 130; and thus, narrow grooves 120 are formed.
At the inner circumferential surface of each of the narrow grooves 120, a gate insulating film 124 is formed, and polysilicon is filled within the narrow groove 120 while the gate insulating film keeps the polysilicon from contacting the substrate to be processed 110. The polysilicon forms a gate electrode plug 127.
The gate electrode plugs 127 in the narrow grooves 120 are connected with one another by a gate electrode film of a thin metal film that is not shown.
On the surfaces of the source diffusion region 130 and the Ohmic diffusion region 116, a source electrode film 137 of a thin metal film is formed. An interlayer insulating film 131 is formed on the narrow grooves 120, and the source electrode film 137 and the gate electrode plugs 127 are electrically insulated from one another by the interlayer insulating film 131.
On the back surface of the substrate to be processed 110 (i.e., on the surface of the semiconductor substrate 111), a drain electrode film 139 is formed.
When a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode film while the source electrode film 137 is connected to the ground potential and a positive voltage is applied to the drain electrode film 139, an n-type inversion layer is formed at the interface between the gate insulating film 124 and the body layer 113. The inversion layer connects the source diffusion region 130 and the drain layer 112 and a current flow from the drain layer 112 to the source diffusion region 130 through the inversion layer. In this state, the transistor 102 conducts; and since there is no JFET region that would exist in a power MOSFET without such narrow grooves 120, the conduction resistance is small as compared to an ordinary power MOSFET.
When the potential of the gate electrode film is pulled to the potential of the source electrode film 137 from the conduction state, the inversion layer disappears and current no longer flows.
In this state, the pn junction between the body layer 113 and the drain layer 112 is reversely biased; and the avalanche breakdown voltage of the pn junction is equal to the withstand voltage of the transistor 102.
In general, the avalanche breakdown voltage of the pn junction varies depending on the shape of a depletion layer during reverse-biasing; and in the transistor 102 as described above, the electric field intensity in the depletion layer expanding in the drain layer 112 is not uniform so that the avalanche breakdown voltage is determined based on the part where the electric field is intensified, which lowers the withstand voltage.
A semiconductor device 103 having a structure as shown in FIG. 42 has been suggested, in which a conductive buried region 122 of a conductivity type different from that of the drain layer 112 is formed under the narrow groove 120 in an attempt to relax the electric field of the depletion layer expanding within the drain layer 112.
The buried region 122 is formed by making narrow grooves 120 having a large depth and then filling a filler by growth at the bottom and side walls of the narrow grooves 120, and the filler may be a single crystal or polycrystal of semiconductor.
However, when the buried region 122 is at a floating potential, the withstand voltage is not stable. When the withstand voltage was obtained by simulations, it was found that the withstand voltage was raised by short-circuiting between the buried region 122 and the source electrode film 137. Specific features for the purpose have been sought after.
Above-mentioned related art is disclosed in Japanese Patent Laid-Open Publication No. 2003-069017